module div3(clock,rst,clk_out3);//5ms
input clock,rst;
output clk_out3;
reg [17:0] m;
reg clk_out3;
always @(posedge clock)
begin
	if(!rst)
	begin clk_out3<=0; m<=0; end
	else
	begin
		m<=m+1;
		if(m==124999) clk_out3<=~clk_out3;
		if(m==249999) begin clk_out3<=~clk_out3; m<=0; end
	end
end

endmodule
